A Low Area FIR Filter For FPGA Implementation

被引：0
|
作者：
Damian, Catalin [1 ]
Lunca, Eduard [1 ]
机构：
[1] Gh Asachi Tech Univ Iasi, Fac Elect Engn, Iasi 700050, Romania
来源：
2011 34TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP) | 2011年
关键词：
FIR filter; FPGA; SOPOT;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a high speed and low area architecture for the implementation of a FIR (Finite Impulse Response) filter into a Field Programmable Gate Array (FPGA) device. The new FIR filter type is implemented with no multiplication block, using only adders and shifting registers. This is possible because a coefficient approximation is performed, using an algorithm that computes the coefficients like a sum-of-power-of-two terms.
引用
收藏
页码：521 / 524
页数：4
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