A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS

被引：0
|
作者：
Kraemer, Martin [1 ]
Janssen, Erwin [2 ]
Doris, Kostas [2 ]
Murmann, Boris [1 ]
机构：
[1] Stanford Univ, Stanford, CA 94305 USA
[2] NXP Semicond, Eindhoven, Netherlands
来源：
2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2015年 / 58卷
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
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页码：284 / U400
页数：3
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