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- [2] A 13 bit 100 MS/s SAR ADC With 74.57 dB SNDR in 14-nm CMOS FinFET 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
- [5] A Dual-Channel 10b 80MS/s Pipeline ADC with 0.16mm2 Area in 65nm CMOS 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 272 - 273
- [6] A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS 2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2015, 58 : 284 - U400
- [7] A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS 2020 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2020,
- [8] A 1.5mW 68dB SNDR 80MS/s 2x Interleaved SAR-Assisted Pipelined ADC in 28nm CMOS 2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 200 - +
- [9] A 95dB SNDR Audio ΔΣ Modulator in 65nm CMOS 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,
- [10] A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR 2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019,