A 12b 61dB SNDR 300MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14nm CMOS FinFET

被引：0

作者：

Luu, Danny ^{[1
,2
]}

Kull, Lukas ^{[2
]}

Toifl, Thomas ^{[2
]}

Menolfi, Christian ^{[2
]}

Braendli, Matthias ^{[2
]}

Francese, Pier Andrea ^{[2
]}

Morf, Thomas ^{[2
]}

Kossel, Marcel ^{[2
]}

Yueksel, Hazar ^{[2
]}

Cevrero, Alessandro ^{[2
]}

Ozkaya, Ilter ^{[2
]}

Huang, Qiuting ^{[1
]}

机构：

[1] Swiss Fed Inst Technol, Zurich, Switzerland

[2] IBM Res Zurich, Ruschlikon, Switzerland

来源：

2017 SYMPOSIUM ON VLSI CIRCUITS | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8V(pp, diff) input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply, where 3.7mW is contributed by the reference buffer.

引用

页码：C276 / C277

页数：2

共 18 条

[1] A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET
Luu, Danny
Kull, Lukas
Toifl, Thomas
Menolfi, Christian
Brandli, Matthias
Francese, Pier Andrea
Morf, Thomas
Kossel, Marcel
Yueksel, Hazar
Cevrero, Alessandro
Ozkaya, Ilter
Huang, Qiuting
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (11) : 3268 - 3279
[2] A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (12) : 4674 - 4678
[3] A 13 bit 100 MS/s SAR ADC With 74.57 dB SNDR in 14-nm CMOS FinFET
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[4] A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS
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[5] A 10-b 2b/cycle 300MS/s SAR ADC with a Single Differential DAC in 40nm CMOS
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[6] A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
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[7] A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching
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[8] A 12b 70MS/s SAR ADC with Digital Startup Calibration in 14 4nm CMOS
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[9] A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
Kull, Lukas
Luu, Danny
Menolfi, Christian
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Francese, Pier Andrea
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2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 474 - 474
[10] A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS
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Janssen, Erwin
Doris, Kostas
Murmann, Boris
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (12) : 2891 - 2900

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