A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

被引:3
|
作者
Lue, HT [1 ]
Hsieh, KY [1 ]
Liu, R [1 ]
Lu, CY [1 ]
机构
[1] Macronix Int Co Ltd, Emerging Cent Lab, Hsinchu 300, Taiwan
关键词
band-to-band tunneling induced hot-electron (BTBTHE); NROM; nitride trapping; P-channel; SONOS;
D O I
10.1109/LED.2005.852742
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P+-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (> 5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (> 10 Mb/sec).
引用
收藏
页码:583 / 585
页数:3
相关论文
共 50 条
  • [21] Low-voltage, fast-programming P-channel flash memory with JVD tunneling nitride
    She, M
    King, TJ
    Hu, CM
    Zhu, WJ
    Luo, ZJ
    Han, JP
    Ma, TP
    2001 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, PROCEEDINGS, 2001, : 641 - 644
  • [22] Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory
    Yeh, Mu-Shih
    Wu, Yung-Chun
    Chung, Ming-Hsien
    Jhan, Yi-Ruei
    Chang-Liao, Kuei-Shu
    Liu, Kuan-Cheng
    Wu, Min-Hsin
    Hung, Min-Feng
    APPLIED PHYSICS LETTERS, 2014, 105 (04)
  • [23] Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology
    Ambatiello, A
    Deichler, J
    MICROELECTRONICS RELIABILITY, 2001, 41 (12) : 1915 - 1921
  • [24] Novel SONOS-type nonvolatile memory device with optimal al doping in HfAlO charge-trapping layer
    Tsai, Ping-Hung
    Chang-Liao, Kuei-Shu
    Liu, Chu-Yung
    Wang, Tien-Ko
    Tzeng, P. J.
    Lin, C. H.
    Lee, L. S.
    Tsai, M. -J.
    IEEE ELECTRON DEVICE LETTERS, 2008, 29 (03) : 265 - 268
  • [25] Novel SONOS-type nonvolatile memory device with suitable band offset in HfAlO charge-trapping layer
    Tsai, Ping-Hung
    Chang-Liao, Kuei-Shu
    Liu, Chu-Yung
    Wang, Tien-Ko
    Tzeng, P. J.
    Lee, L. S.
    Tsai, M. J.
    2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 20 - +
  • [26] Characterization of the charge trapping properties in p-channel silicon-oxide-nitride-oxide-silicon memory devices including SiO2/Si3N4 interfacial transition layer
    Chiu, Yung-Yueh
    Yang, Bo-Jun
    Li, Fu-Hai
    Chang, Ru-Wei
    Sun, Wein-Town
    Lo, Chun-Yuan
    Hsu, Chia-Jung
    Kuo, Chao-Wei
    Shirota, Riichiro
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2015, 54 (10)
  • [27] Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure
    Cho, Il Hwan
    Park, Tai-Su
    Choe, Jeong Dong
    Cho, Hye Jin
    Park, Donggun
    Shin, Hyungcheol
    Park, Byung-Gook
    Lee, Jong Duk
    Lee, Jong-Ho
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2006, 24 (03): : 1266 - 1270
  • [28] Novel self-convergent programming scheme for multi-level P-channel flash memory
    Shen, SJ
    Yang, CS
    Wang, YS
    Hsu, CCH
    Chang, SD
    Rodjy, N
    Wang, AC
    INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 287 - 290
  • [29] A novel p-channel flash electrically-erasable programmable read-only memory (EEPROM) cell with oxide-nitride-oxide (ONO) as split gate channel dielectric
    Huang, CJ
    Liu, YC
    Wang, MC
    Caywood, J
    Hong, SF
    Wu, A
    Hsia, LC
    Chang, YJ
    Liu, FT
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2001, 40 (4B): : 2943 - 2947
  • [30] Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure
    Wei, Jiaxing
    Liu, Siyang
    Liu, Xiaoqiang
    Sun, Weifeng
    Liu, Yuwei
    Liu, Xiaohong
    Hou, Bo
    SOLID-STATE ELECTRONICS, 2017, 134 : 58 - 64