SILC Degradation Model to Predict Area Scaling for Gate Dielectric Breakdown in Advanced Technologies

High-K metal gate stack with bi-modal distribution provides the TDDB benefit in product usage condition at low percentile and large area. As the technology continues to scale, the precise area scaling projection is becoming important to provide necessary overdrive for circuit operation. A degradation rate based Monte-Carlo simulator is developed for the first time to predict NMOSFET TDDB degradation to product area based on two distinct degradation regimes, namely progressive regime with SILC increase due to trap generation in HK, followed by the thermal runaway regime leading to rapid current increase. The model is validated against experimental data and is shown to predict TDDB degradation for different gate oxide area, stress bias & process variation. Impact of Weibull slope and MTTF on area scaling ratio is also discussed. Finally it is shown that for an optimized process, the model can provide 50X higher lifetime at product usage condition as compared to conventional area scaling model, thus providing much needed headroom for overdrive in advanced technologies.