Development of Developer-Soluble Gap Fill Materials for Planarization in Via-First Dual Damascene Process

被引:2
|
作者
Takei, Satoshi [1 ]
Sakaida, Yasushi [1 ]
Ishii, Kazuhisa [1 ]
Shinjo, Tetsuya [1 ]
机构
[1] Nissan Chem Ind Co Ltd, Elect Mat Res Labs, Toyama 9392792, Japan
关键词
lithography; gap fill materials; planarization; etch rate; dual damascene;
D O I
10.1143/JJAP.47.3412
中图分类号
O59 [应用物理学];
学科分类号
摘要
Gap fill materials and planar-type bottom antireflective coating are needed for patterning metal trenches in the via-first dual damascene process. We have already reported on thermal cross-link gap fill materials and bottom antireflective coating as planarizing layers under a resist that can be spin-coated and etched faster than resists. In this study, developer-soluble gap fill materials were optimized in order to obtain excellent planarization, simplify the process, and increase wafer throughput. The developer-soluble gap fill materials using poly(4-hydroxystyrene) derivatives developed by an approach of the via-first dual damascene process was obtained by optimizing the concentration of the phenol group with solubility in the alkaline developer (0.26 N tetramethylammonium hydroxide, TMAH) and by thermal cross-link reaction. In addition to a superior via-filling performance, developer-soluble gap fill materials using poly(4-hydroxystyrene) derivatives showed a wide process window of prebake temperature, the controllable dissolution rate for the etch-back process, and a good CF(4) etch rate of 1.4 times higher than that of a resist for etching the substrate. These results were attributed to the polymer structures of poly(4-hydroxystyrene) derivatives. Both dry plasma cleaning and wet developer cleaning can be used to remove residual gap fill materials after processing. This novel approach using developer-soluble gap fill materials as a new type of sacrificial material in an advanced lithography process makes this solution convenient for planarizing surfaces and is economically favorable owing to high throughput. [DOI: 10.1143/JJAP.47.3412]
引用
收藏
页码:3412 / 3417
页数:6
相关论文
共 37 条
  • [1] Development of developer-soluble gap fill materials for planarization in via-first dual damascene process
    Takei, Satoshi
    Sakaida, Yasushi
    Ishii, Kazuhisa
    Shinjo, Tetsuya
    Japanese Journal of Applied Physics, 2008, 47 (5 PART 1): : 3412 - 3417
  • [2] Developer-soluble gap fill materials for patterning metal trenches in via-first dual damascene process
    Bhave, M
    Edwards, K
    Washburn, C
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXI, PTS 1 AND 2, 2004, 5376 : 640 - 647
  • [3] Wet-recess process optimization of a developer-soluble gap-fill material for planarization of trenches in trench-first dual damascene process
    Washburn, Carlton
    Brakensiek, Nick
    Guerrero, Alice
    Edwards, Kevin
    Stroud, Charlyn
    Chapman, Nicki
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXIII, PTS 1 AND 2, 2006, 6153 : U1063 - U1068
  • [4] Characterization of gap fill materials for planarizing substrate in via-first dual damascene lithography process
    Takei, Satoshi
    Sakaida, Yasushi
    Shinjo, Tetsuya
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (9A): : 5755 - 5761
  • [5] Characterization of gap fill materials for planarizing substrate in via-first dual damascene lithography process
    Takei, Satoshi
    Sakaida, Yasushi
    Shinjo, Tetsuya
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2007, 46 (9 A): : 5755 - 5761
  • [6] Resist Poisoning Studies of Gap Fill Materials for Patterning Metal Trenches in Via-First Dual Damascene Process
    Takei, Satoshi
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (12) : 8766 - 8770
  • [7] Advanced developer-soluble gap-fill materials and applications
    Huang, Runhui
    Sullivan, Dan
    Qin, Anwei
    Brown, Shannon
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXIV, 2007, 6519
  • [8] Planarization approaches to via-first dual-damascene processing
    Pavelchek, EK
    Cernigliaro, M
    Trefonas, P
    doCanto, M
    CHALLENGES IN PROCESS INTEGRATION AND DEVICE TECHNOLOGY, 2000, 4181 : 140 - 151
  • [9] Focus error reduction by photo-resist planarization in via-first dual damascene process
    Matsui, Y
    Minamihaba, G
    Tateyama, Y
    Takahata, K
    Shigeta, A
    Nishioka, T
    Yano, H
    Hayasaka, N
    PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 162 - 164
  • [10] Process sensitivity and robustness analysis of via-first dual-damascene process
    Tsui, BY
    Chen, CW
    Huang, SM
    Lin, SS
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2003, 16 (02) : 307 - 313