GA Based Selective Harmonic Elimination for Multilevel Inverter with Reduced Number of Switches

被引：0

作者：

Karaca, Hulusi ^{[1
]}

Bektas, Enes ^{[2
]}

机构：

[1] Selcuk Univ, Fac Technol, Dept Elect & Elect Engn, TR-42075 Konya, Turkey

[2] Univ Cankin Karatekin, Fac Engn & Architecture, Dept Elect & Elect Engn, Cankiri, Turkey

来源：

WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2015, VOL I | 2015年

关键词：

Genetic algorithm; minimum number of switches; multilevel inverter; selective harmonic elimination; total harmonic distortion;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Multilevel inverters have been used in the power applications to get low total harmonic distortion (THD) in medium or high voltage levels. In order to get low THD in the output voltage, several techniques have been applied to multilevel inverter. One of these techniques is Selective Harmonic Elimination (SHE) that has an extensive research area in the field of power electronics. It is also an alternative to usual PWM techniques and includes nonlinear equations of stepped voltage waveform. In this paper, multilevel inverter with reduced number of switches which enables a reduction in the system cost has been proposed, and solution of SHE equations have been optimized by Genetic Algorithm (GA). The results of simulation and analysis have apparently proved that proposed GA based SHE technique eliminates desired harmonic order.

引用

页码：204 / 209

页数：6

共 50 条

[21] Multilevel Single Phase Isolated Inverter with Reduced Number of Switches
Verdugo, Cristian
Candela, Jose I.
Elsaharty, Mohamed A.
Rodriguez, Pedro
2018 7TH INTERNATIONAL CONFERENCE ON RENEWABLE ENERGY RESEARCH AND APPLICATIONS (ICRERA), 2018, : 1202 - 1208
[22] A Novel Cascaded Asymmetrical Multilevel Inverter With Reduced Number of Switches
Boora, Kamaldeep
Kumar, Jagdish
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2019, 55 (06) : 7389 - 7399
[23] Cascaded multilevel inverter with regeneration capability and reduced number of switches
Lezana, Pablo
Rodriguez, Jose
Oyarzun, Diego A.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2008, 55 (03) : 1059 - 1066
[24] Simulation Analysis of New Multilevel Inverter with Reduced Number of Switches
Dhivakar, K.
Thiyagarajan, V
2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2018, : 443 - 448
[25] A New Multilevel Inverter Topology with Reduced Number of Power Switches
Beigi, L. M. A.
Azli, N. A.
Khosravi, F.
Najafi, E.
Kaykhosravi, A.
2012 IEEE INTERNATIONAL CONFERENCE ON POWER AND ENERGY (PECON), 2012, : 55 - 59
[26] General topology for asymmetrical multilevel inverter with reduced number of switches
Boora, Kamaldeep
Kumar, Jagdish
IET POWER ELECTRONICS, 2017, 10 (15) : 2034 - 2041
[27] A New Hybrid Asymmetric Multilevel Inverter with Reduced Number Of Switches
Prabaharan, N.
Palanisamy, K.
2016 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES), 2016,
[28] Performance Investigation of Sub Multilevel Inverter with Reduced Number of Switches
Sowjanya, Thaticharla
Veerendranath, K.
2018 NATIONAL POWER ENGINEERING CONFERENCE (NPEC), 2018,
[29] A New Three Phase Multilevel Inverter Topology with Reduced Number of Switches with Common Mode Voltage Elimination
Hota, Arpan
Jain, Sachin
PROCEEDINGS OF THE FIRST IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, INTELLIGENT CONTROL AND ENERGY SYSTEMS (ICPEICES 2016), 2016,
[30] Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology
Sarika D. Patil
Sumant G. Kadwane
Microsystem Technologies, 2018, 24 : 3409 - 3415

← 1 2 3 4 5 →