Power-efficient VLSI realization of a complex FSM for H.264/AVC bitstream parsing

被引：1

作者：

Xu, Ke ^{[1
]}

Choy, Chiu-Sing ^{[1
]}

Chan, Cheong-Fat ^{[1
]}

Pun, Kong-Pang ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Elect Engn, Sha Tin, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 11期

关键词：

clock gating; decoding; finite state machine (FSM); hierarchical; power efficient;

D O I：

10.1109/TCSII.2007.903785

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a systematic, power-efficient design methodology for the complex finite state machine (FSM) implementation of H.264/AVC decoding. The proposed FSM orchestrates the decoding steps and predicts the type of incoming codeword based on current FSM states and input symbols. The VLSI realization shows a gate count reduction of 14% and an average power reduction of 37.6% in real-time video decoding. The FSM has been implemented with UMC130 nm 1P6M CMOS technology, and it consumes 38.3 mu W at 1.08 V when running at 20 MHz.

引用

页码：984 / 988

页数：5

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