GaAs multiplier and adder designs for high-speed DSP applications

This paper describes two designs in 0.6 mu m Gallium Arsenide MESFET technology of arithmetic primitives widely used in high-speed DSP integrated circuits. The two designs are: 16x16-bit multiplier simulated delay = 2.4ns 32-bit adder measured delay = 1.3 ns These speeds were achieved at a 0.9 V power supply and the delays quoted are non-pipelined so that the latency is 1. The power dissipation for both designs was found to be less than 0.5 mu W/gate/MHz. Both designs use a layout technique called "Modified Ring Notation" that improves the packing density of these chips compared to previous designs using Ring Notation. The paper presents issues raised in the architecture designs such as minimising wire lengths, compacting the cell layouts, sizing the transistors, and introducing buffers to minimise fan-out loading on the critical path.