A 250MHz optimized distributed architecture of 2D 8x8 DCT

被引：0

作者：

Peng Chungan ^{[1
]}

Cao Xixin ^{[1
]}

Yu Dunshan ^{[1
]}

Zhang Xing ^{[1
]}

机构：

[1] Peking Univ, Dept Microelect, SOC Lab, Beijing 100871, Peoples R China

来源：

ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Discrete Cosine Transform (DCT) plays an important role in image and video compression, but computing a two-dimensional (2D) DCT, a large number of multiplications and additions are required in a direct approach. Multiplications, which are the most time-consuming and expensive operations in simple processor, can be completely avoided in our proposed architecture for multiple channel real-time image compression. In this paper, a compressed distributed arithmetic architecture for 2D W DCT is presented, which offers high speed and small area. The basic architecture consists of a ID row DCT followed by a transpose register array and another I D column DCT, in which an 8-input ID DCT structure only requires 15 adders to build a compressed adder matrix and no ROM is needed. Compared with other architectures available it, has a great improvement on computing speed and reducing area.

引用

页码：189 / 192

页数：4

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