A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7nm FinFET CMOS

被引：0

作者：

Kuan, Ting-Kuei ^{[1
]}

Wu, Chin-Yang ^{[1
]}

Shen, Ruei-Pin ^{[1
]}

Chang, Chih-Hsien ^{[1
]}

Hsieh, Kenny ^{[1
]}

Chen, Mark ^{[1
]}

机构：

[1] TSMC, Hsinchu, Taiwan

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a digital bang-bang phase-locked loop that employs background injection timing calibration and automatic loop gain control to enhance the jitter and spur performance against PVT variations. The chip is fabricated in 7nm FinFET technology. This bang-bang phase-locked loop achieves 426.5fs(rms) integrated jitter and -61dBc reference spurs, occupying an area of 0.018mm(2) (120 mu x 150 mu m). The FOM is -239.4dB at 4GHz output frequency.

引用

页码：179 / 180

页数：2

共 40 条

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