A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7nm FinFET CMOS

被引：0

作者：

Kuan, Ting-Kuei ^{[1
]}

Wu, Chin-Yang ^{[1
]}

Shen, Ruei-Pin ^{[1
]}

Chang, Chih-Hsien ^{[1
]}

Hsieh, Kenny ^{[1
]}

Chen, Mark ^{[1
]}

机构：

[1] TSMC, Hsinchu, Taiwan

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a digital bang-bang phase-locked loop that employs background injection timing calibration and automatic loop gain control to enhance the jitter and spur performance against PVT variations. The chip is fabricated in 7nm FinFET technology. This bang-bang phase-locked loop achieves 426.5fs(rms) integrated jitter and -61dBc reference spurs, occupying an area of 0.018mm(2) (120 mu x 150 mu m). The FOM is -239.4dB at 4GHz output frequency.

引用

页码：179 / 180

页数：2

共 40 条

[1] A Digital Bang-Bang Phase-Locked Loop with Automatic Loop Gain Control and Loop Latency Reduction
Kuan, Ting-Kuei
Liu, Shen-Luan
2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS), 2015,
[2] A Digital Bang-Bang Phase-Locked Loop with Bandwidth Calibration
Chiang, Chi-Huan
Huang, Chang-Cheng
Liu, Shen-Iuan
2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2015, : 173 - 176
[3] A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
Kuan, Ting-Kuei
Liu, Shen-Iuan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (04) : 821 - 831
[4] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Jincheng Yang
Zhao Zhang
Nan Qi
Liyuan Liu
Jian Liu
Nanjian Wu
Journal of Semiconductors, 2018, 39 (12) : 172 - 178
[5] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Jincheng Yang
Zhao Zhang
Nan Qi
Liyuan Liu
Jian Liu
Nanjian Wu
Journal of Semiconductors, 2018, (12) : 172 - 178
[6] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Yang, Jincheng
Zhang, Zhao
Qi, Nan
Liu, Liyuan
Liu, Jian
Wu, Nanjian
JOURNAL OF SEMICONDUCTORS, 2018, 39 (12)
[7] An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs
Kwon, Soon-Won
Lee, Joon-Yeong
Lee, Jinhee
Han, Kwangseok
Kim, Taeho
Lee, Sangeun
Lee, Jeong-Sup
Yoon, Taehun
Won, Hyosup
Park, Jinho
Bae, Hyeon-Min
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (12) : 2817 - 2828
[8] Digital Phase Locked Loop (DPLL) with Offset Dithered Bang-Bang Phase Detector (BBPD) for Bandwidth Control
Kim, Younghoon
Jeon, Min-Ki
Yoo, Changsik
2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 79 - 82
[9] A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm
Hung, Chao-Ching
Liu, Shen-Iuan
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (06) : 321 - 325
[10] Combined Effect of Loop Delay and Reference Clock Jitter in First-Order Digital Bang-Bang Phase-Locked Loops
Tertinek, Stefan
Feely, Orla
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2393 - 2396

← 1 2 3 4 →