FPGA Implementation of BCH Decoder for Memory Systems

被引：0

作者：

Chandrashekhara, B. S. ^{[1
]}

Sudha, K. L. ^{[1
]}

机构：

[1] Dayananda Sagar Coll Engn, Dept ECE, Bangalore, Karnataka, India

来源：

PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON APPLIED AND THEORETICAL COMPUTING AND COMMUNICATION TECHNOLOGY (ICATCCT) | 2015年

关键词：

BCH codes; Double-adjacent error correction (DAEC); Error correcting code (ECC); Parallel decoder; Shortened BCH codes; LOW-COST; ERROR;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to detect and correct the errors in communication system and also on-chip (computer) memory systems. This paper presents a High-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors instead of double-adjacent errors. Its operation is based on extending an existing decoder that corrects only single-bit errors in parallel and serially corrects double-adjacent errors at low speed. The proposed constructed decoder design is suitable for nanoscale memory systems, in which double-adjacent and single-bit errors occur at a higher probability compared to the multiple-bit errors. This paper also shows that the area and delay overheads incurred by the proposed scheme are significantly lower than traditional BCH decoders capable of correcting any double-bit errors in parallel.

引用

页码：542 / 547

页数：6

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