65nm-node low-k/Cu interconnect in "Asuka" project - Porous low-k for manufacturing

The 65nm node low-k/Cu interconnect which has been developed in "Asuka" project is reviewed. Key technologies for porous low-k process are discussed to reinforce the mechanical, deposition, and plasma damage during the fabrication process. The feasibility of those processes has been verified through the 200 nm-pitch Cu/porous low-k interconnect integration in the 300 mm CMOS fabrication lines. Importance of material and process continuity from the 90nm node to the 65 nm node is discussed in terms of porous low-k for manufacturing.