65nm-node low-k/Cu interconnect in "Asuka" project - Porous low-k for manufacturing

被引：0
|
作者：
Kobayashi, N [1 ]
机构：
[1] Semicond Leading Edge Technol Inc, Tsukuba, Ibaraki 3058569, Japan
来源：
ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004) | 2004年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The 65nm node low-k/Cu interconnect which has been developed in "Asuka" project is reviewed. Key technologies for porous low-k process are discussed to reinforce the mechanical, deposition, and plasma damage during the fabrication process. The feasibility of those processes has been verified through the 200 nm-pitch Cu/porous low-k interconnect integration in the 300 mm CMOS fabrication lines. Importance of material and process continuity from the 90nm node to the 65 nm node is discussed in terms of porous low-k for manufacturing.
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页码：3 / 14
页数：12
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