FinFET source/drain profile optimization considering GIDL for low power applications

被引：1

作者：

Tanaka, K ^{[1
]}

Takeuchi, K ^{[1
]}

Hane, M ^{[1
]}

机构：

[1] NEC Corp Ltd, Syst Devices Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

SISPAD: 2005 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2005年

关键词：

D O I：

10.1109/SISPAD.2005.201528

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have investigated sub-50mn FinFET design to be used in low power applications, through 3D device simulations considering gate-induced drain leakage (GIDL). It is found that the body-tied structure is necessary for dopedchannel FinFET to reduce off-state current (I-off). For further reduction of I-off including GIDL, optimization of source/drain (S/D) profile characterized by lateral spread sigma and lateral offset delta is effective, and feasibility of S/D profile depends on channel doping concentration. By adjusting the concentration properly, I-off can be reduced for (sigma, delta) points in a wide range. In addition, sensitivity of drive current upon sigma and delta is found to be small.

引用

页码：283 / 286

页数：4

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