Transition Skew Coding for global on-chip interconnect

被引：4

作者：

Akl, Charbel J. ^{[1
]}

Bayoumi, Magdy A. ^{[1
]}

机构：

[1] Univ Louisiana Lafayette, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2008年 / 16卷 / 08期

关键词：

crosstalk; power; repeater; routing; wire;

D O I：

10.1109/TVLSI.2008.2000596

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents new simulation results of the previously proposed Transition Skew Coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.

引用

页码：1091 / 1096

页数：6

共 50 条

[41] On-chip optical interconnect using visible light
Cai, Wei
Zhu, Bing-cheng
Gao, Xu-min
Yang, Yong-chao
Yuan, Jia-lei
Zhu, Gui-xia
Wang, Yong-jin
Grunberg, Peter
FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2017, 18 (09) : 1288 - 1294
[42] Materials and devices for silicon on-chip optical interconnect
Ballantyne, JM
ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 83 - 87
[43] On-chip interconnect inductance - Friend or foe (invited)
Wong, SS
Yue, P
Chang, R
Kim, SY
Kleveland, B
O'Mahony, F
4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 389 - 394
[44] Layout techniques for on-chip interconnect inductance reduction
Tu, SW
Jou, JY
Chang, YW
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 269 - 273
[45] On-chip optical interconnect on silicon by transfer printing
Liu, Lei
Loi, Ruggero
Roycroft, Brendan
O'Callaghan, James
Justice, John
Trindade, Antonio Jose
Kelleher, Ste En
Gocalinska, Agnieszka
Thomas, Kevin
Pelucchi, Emanuele
Bower, Christopher A.
Corbett, Brian
2018 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2018,
[46] Leakage-aware interconnect for on-chip network
Tsai, YF
Narayaynan, V
Xie, Y
Irwin, MJ
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 230 - 231
[47] GaN directional couplers for on-chip optical interconnect
Yuan, Jialei
Gao, Xumin
Yang, Yongchao
Zhu, Guixia
Yuan, Wei
Choi, Hoi Wai
Zhang, Zhiyu
Wang, Yongjin
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2017, 32 (04)
[48] A Convolutional Code for On-chip Interconnect Crosstalk Reduction
Courtay, Antoine
Boutillon, Emmanuel
Laurent, Johann
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 145 - 148
[49] TrafficLite: A Configurable On-Chip Interconnect Router Microarchitecture
Xie Bin
Fu Weiwei
Chen Tian-zhou
2012 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2012 IEEE 9TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (HPCC-ICESS), 2012, : 501 - 508
[50] Packetized on-chip interconnect communication analysis for MPSoC
Ye, TT
Benini, L
De Micheli, G
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 344 - 349

← 1 2 3 4 5 →