Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier

被引:11
|
作者
Peroni, Daniel [1 ]
Imani, Mohsen [1 ]
Rosing, Tajana Simuni [1 ]
机构
[1] Univ Calif San Diego, Dept Comp Sci & Engn, La Jolla, CA 92093 USA
关键词
Approximate computing; energy efficiency; floating point unit (FPU); GPU;
D O I
10.1109/TCAD.2018.2885317
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Many applications, such as machine learning and sensor data analysis, are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computing is a viable method to save energy and increase performance by controllably trading off energy for accuracy. In this paper, we propose a tiered approximate floating point multiplier, called CFPU, which significantly reduces energy consumption and improves the performance of multiplication at a slight cost in accuracy. The floating point multiplication is approximated by replacing the costly mantissa multiplication step of the operation with lower energy alternatives. We process the data by using one of the three modes: a basic approximate mode, an intermediate approximate mode, or on the exact hardware, depending on the accuracy requirements. We evaluate the efficiency of the proposed CFPU on a wide range of applications including twelve general OpenCL ones and three machine learning applications. Our results show that using the first CFPU approximation mode results in 3.5x energy-delay product (EDP) improvement, compared to a GPU using traditional floating point units (FPUs), while ensuring less than 10% average relative error. Adding the second mode further increases the EDP improvement to 4.1x, compared to an unmodified FPU, for less than 10% error. In addition, our results show that the proposed CFPU can achieve 2.8x EDP improvement for multiply operations as compared to state-of-the-art approximate multipliers.
引用
收藏
页码:346 / 358
页数:13
相关论文
共 50 条
  • [21] Software Acceleration of Floating-point Multiplication using Runtime Code Generation
    Aracil, Charles
    Courousse, Damien
    2013 4TH ANNUAL INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS AND APPLICATIONS (ICEAC), 2013, : 18 - 23
  • [22] ANALYSIS OF FLOATING POINT ROUNDOFF ERRORS USING DUMMY MULTIPLIER COEFFICIENT SENSITIVITIES
    BING, Z
    NEUVO, Y
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1991, 38 (06): : 590 - 601
  • [23] FFT Implementation Using Floating Point Fused Multiplier with Four Term Adder
    Baboji, K.
    Sridevi, Sriadibhatla
    2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS), 2017,
  • [24] High-Speed Single Precision Floating Point Multiplier using CORDIC Algorithm
    Yeshwanth, Balaji
    Venkatesh, Vutukuri
    Akhil, Repala
    2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018), 2018, : 135 - 141
  • [25] IMPLEMENTATION OF 16-BIT FLOATING POINT MULTIPLIER USING RESIDUE NUMBER SYSTEM
    Samhitha, Naamatheertham R.
    Cherian, Neethu Acha
    Jacob, Pretty Mariam
    Jayakrishnan, P.
    2013 INTERNATIONAL CONFERENCE ON GREEN COMPUTING, COMMUNICATION AND CONSERVATION OF ENERGY (ICGCE), 2013, : 195 - 198
  • [26] Using delayed addition techniques to accelerate integer and floating-point calculations in configurable hardware
    Luo, Z
    Martonosi, M
    CONFIGURABLE COMPUTING: TECHNOLOGY AND APPLICATIONS, 1998, 3526 : 202 - 211
  • [27] Efficiency and Accuracy Improvements of Secure Floating-Point Addition over Secret Sharing
    Sasaki, Kota
    Nuida, Koji
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2022, E105A (03) : 231 - 241
  • [28] Efficiency and Accuracy Improvements of Secure Floating-Point Addition over Secret Sharing
    Sasaki, Kota
    Nuida, Koji
    ADVANCES IN INFORMATION AND COMPUTER SECURITY (IWSEC 2020), 2020, 12231 : 77 - 94
  • [29] Modeling Point Spread Function in Fluorescence Microscopy With a Sparse Gaussian Mixture: Tradeoff Between Accuracy and Efficiency
    Samuylov, Denis K.
    Purwar, Prateek
    Szekely, Gabor
    Paul, Gregory
    IEEE TRANSACTIONS ON IMAGE PROCESSING, 2019, 28 (08) : 3688 - 3702
  • [30] Design of High Performance IEEE754 Floating Point Multiplier Using Vedic mathematics
    Mahakalkar, Sushma S.
    Haridas, Sanjay L.
    2014 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS, 2014, : 985 - 988