A PVT Invariant Cascode Current Reference Circuit in 180nm CMOS Process

This paper presents a PVT invariant cascode current reference circuit implemented in UMC 180 nm CMOS process. In the proposed design the process compensation is achieved by a two-step compensation biasing circuit. The temperature compensation is achieved by the triode transistor and voltage dependency is reduced by cascode structure. The simulations of the circuit are carried out using the Cadence Virtuoso tool. From the simulations, it is observed that the reference current value of the circuit is 12.42 mu A with the measured temperature coefficient (TC) of 1161ppm/degrees C in the range of -40 degrees C to 100 degrees C, process variation of +/- 6.03 %, and power supply dependency of +/- 4.42 % which is good as compared to the current reference circuits proposed in the literature. The proposed circuit is suitable for easy integration into other CMOS circuits as a reliable current source.