Advanced Gate and Stack Dielectric Characterization with FastGate® Technology

被引：0

作者：

Hillard, Robert J. ^{[1
]}

Tan, Louison C. ^{[1
]}

Reid, Kimberly G. ^{[2
]}

机构：

[1] Solid State Measurements Inc, 110 Technol Dr, Pittsburgh, PA 15275 USA

[2] Tokyo Elect Amer, Austin, TX 78741 USA

来源：

FRONTIERS OF CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2009 | 2009年 / 1173卷

关键词：

Interface Trap Density; Flatband Voltage; EM-Probe; High-k Dielectrics;

D O I：

暂无

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

In this paper a non-damaging and non-contaminating method for performing Capacitance-Voltage (CV) and Current-Voltage (IV) electrical characterization of advanced gate dielectrics and stack capacitor films is presented. The method uses a contacting Elastic Material Probe (EM-Probe) that is made of a semiconductor compatible material and forms a gate contact diameter of about 30 to 50 microns. Key electrical parameters that are measured are, Capacitive Effective Thickness (CET), Equivalent Oxide Thickness (EOT), Interface Trap Density (D-it) delta V-FB Hysteresis (Delta V-FB), leakage current density (J(LK)), Field-to-breakdown (F-BD), Charge-to-breakdown (Q(BD)) and Stress Induced Leakage Current (SILC). Measurements can be made on either blanket or in scribe line test areas in patterned wafers.

引用

页码：89 / +

页数：2

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