Design Techniques for Ultra Low-Power Phase-Locked Loops

被引：0
|
作者：
Park, Dongmin [1 ]
Cho, SeongHwan [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept EE, Taejon, South Korea
来源：
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2011年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Ultra-low power frequency synthesizers resilient to environmental variations are desired in various wireless microsensor applications where power consumption and reliability are important performance metrics. This paper reviews the design techniques for a ultra-low power PLLs employing low-supply voltage and charge recycling techniques. Design challenges such as minimizing sensitivity to environmental variations are addressed for low-voltage and charge-recycling operation, which include adaptive body-biasing and implicit negative feedback DCDC conversion.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] Low-Power Optimization Design of CMOS Phase-Locked Loop for WiFi-6E Applications
    Kuo, Yue-Fang
    Han, Shuo
    2022 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN, IEEE ICCE-TW 2022, 2022, : 9 - 10
  • [42] Ultra low power phase detector and phase-locked loop designs and their application as a receiver
    Li, Bo
    Zhai, Yiming
    Yang, Bo
    Salter, Thomas
    Peckerar, Martin
    Goldsman, Neil
    MICROELECTRONICS JOURNAL, 2011, 42 (02) : 358 - 364
  • [43] A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature
    Kim, Min Yeong
    Lee, Kang Yoon
    2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 262 - 263
  • [44] Design of a high performance charge pump circuit for low voltage phase-locked loops
    Sun, Yuan
    Sick, Liter
    Song, Pengyu
    2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 271 - 274
  • [45] Phase-Control Techniques for Sub-Sampling Phase-Locked Loops
    Anjos, Eduardo V. P.
    Schreurs, Dominique M. M. -P.
    Vandenbosch, Guy A. E.
    2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,
  • [46] PHASE-LOCKED LOOPS - APPLICATION TO COHERENT RECEIVER DESIGN - BLANCHARD,A
    KLAPPER, J
    IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS, 1980, 10 (08): : 537 - 537
  • [47] Design of high-performance phase-locked loops and synthesizers
    Shahruz, SM
    JOURNAL OF SOUND AND VIBRATION, 2001, 244 (02) : 367 - 377
  • [48] Analysis and design on variable sampling period phase-locked loops
    Zhang, Xiaorui
    Xu, Jinming
    Qian, Qiang
    Xie, Shaojun
    Dianwang Jishu/Power System Technology, 2014, 38 (09): : 2605 - 2610
  • [49] Passivity-based design and analysis of phase-locked loops
    Zonetti, Daniele
    Gomis-Bellmunt, Oriol
    Prieto-Araujo, Eduardo
    Cheah-Mane, Marc
    2022 EUROPEAN CONTROL CONFERENCE (ECC), 2022, : 2075 - 2080
  • [50] Low-Power Optimization Design of 20-bit Digital Shift Register for Phase-Locked Loop Applications
    Kuo, Yue-Fang
    Chen, Wei-Yang
    Chang, Su-Wei
    2024 11TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-TAIWAN, ICCE-TAIWAN 2024, 2024, : 555 - 556
12345