An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection

被引：0
|
作者：
Proesel, Jonathan [1 ]
Keskin, Gokce [1 ]
Plouchart, Jean-Olivier [2 ]
Pileggi, Lawrence [1 ]
机构：
[1] Carnegie Mellon Univ, 5000 Forbes Ave, Pittsburgh, PA 15213 USA
[2] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY USA
来源：
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 | 2010年
关键词：
ANALOG CIRCUITS; CONVERTER; ARCHITECTURES; CALIBRATION; MISMATCH; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An 8-bit, 1.5GS/s flash ADC is presented. Comparators are digitally calibrated using statistical selection. INL of 1.32 LSB and DNL of 1.23 LSB are achieved. Average comparator noise of 5mV(rms) (1.3 LSB) limits SNDR to 37dB at low frequencies. Total power is 35mW, 20mW in the S&H and 15mW in the ADC core. The figure of merit is 0.42pJ/conv, the best reported for 1+GS/s, 7+-bit ADCs.
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页数：4
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