The power consumption reducing technique of the pseudo-random test pattern generator and the signature analyzer for the built-in self-test

This paper presents new solutions for reducing the power consumption BIST environment (Pseudorandom Test Pattern Generator-PTPG and Signature Analyzer-SA). The key idea behind this technique is based on the designing a new structure of LFSR (Linear Feedback Shift Register) to generate more than one pseudo random bit per one clock pulse and a new SA structure for compressing several test responses bits per one clock pulse. The <<proposed method can be used within test per-clock>> BIST architecture, as well as may be extended for the west-per-scan)) BIST technique.