Design of DC offset canceller using parallel compensation

被引：7

作者：

Oh, Seung-Min ^{[1
]}

Park, Kyoung-Seok ^{[1
]}

Yoo, Hyun-Hwan ^{[1
]}

Na, Yoo-Sam ^{[1
]}

Kim, Taek-Soo ^{[1
]}

机构：

[1] Samsung Electromech Co, IC Design Ctr, Suwon 443743, Gyeonggi Do, South Korea

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.377917

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, a new DC offset canceller with parallel compensation is proposed based on the CMOS technology. Compared to the previously reported DC offset cancellers, the proposed topology can be implemented with the lower HPCF(High Pass Cutoff Frequency) in the silicon substrate using same capacitance value. By utilizing the proposed DC offset canceller, an IF-VGA is designed for the direct conversion receiver and shows 1kHz of HPCF and 60dB of gain, while dissipating total current of 9mA from 1.8V supply with output buffer.

引用

页码：1685 / 1688

页数：4

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