Low-power 200-Msps, area-efficient, five-tap programmable FIR filter

被引：11
|
作者：
Moloney, D [1 ]
O'Brien, J
O'Rourke, E
Brianti, F
机构：
[1] Silicon Syst Design Ltd, Dublin 2, Ireland
[2] SGS Thomson Microelect, San Jose, CA 95110 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 07期
关键词：
BiCMOS; booth recoding; FIR; 4 : 2 compressor; hard-disk drive; multiplier; partial product; Wallace tree;
D O I：
10.1109/4.701282
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-sample per cycle, programmable five-tap, area-efficient finite-impulse response (FLR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 mu W/MHz [6] with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques.
引用
收藏
页码：1134 / 1138
页数：5
相关论文
共 50 条
  • [31] Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology
    Kim, Woo Joo
    Hwang, Sun Young
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2008, E91A (11) : 3297 - 3303
  • [32] Embedded Capacitor-Multiplier Compensation for Area-Efficient Low-Power Multistage Amplifiers
    Yan, Zushu
    2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 153 - 156
  • [33] A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure
    Tang, Xiqin
    Li, Yang
    Lin, Chenxiao
    Shang, Delong
    ELECTRONICS, 2022, 11 (17)
  • [34] Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching
    Kim, Woo Joo
    Lee, Sung Hee
    Hwang, Sun Young
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (03) : 890 - 899
  • [35] Low-power and area-efficient PSK demodulator for wirelessly powered implantable command receivers
    Gong, C. -S. A.
    Shiue, M. -T.
    Yao, K. -W.
    Chen, T. -Y.
    ELECTRONICS LETTERS, 2008, 44 (14) : 841 - U162
  • [36] Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors
    Li, Jiayi
    Li, Jingyu
    Ding, Yi
    Liu, Chunsen
    Hou, Xiang
    Chen, Huawei
    Xiong, Yan
    Zhang, David Wei
    Chai, Yang
    Zhou, Peng
    2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
  • [37] Low-power area-efficient design of embedded high-speed A/D converters
    Miyazaki, D
    Kawahito, S
    IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (11): : 1724 - 1732
  • [38] An 8-Channel, Area-Efficient, Low-Power Audio Sampling Rate Converter
    Kuang, Haipeng
    Wang, Dejiang
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 21 - 24
  • [39] Low-power area-efficient high-speed I/O circuit techniques
    Lee, MJE
    Dally, WJ
    Chiang, P
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) : 1591 - 1599
  • [40] Towards Generic Low-Power Area-Efficient Standard Cell Based Memory Architectures
    Meinerzhagen, P.
    Roth, C.
    Burg, A.
    53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 129 - 132
12345