Low-power 200-Msps, area-efficient, five-tap programmable FIR filter

被引：11
|
作者：
Moloney, D [1 ]
O'Brien, J
O'Rourke, E
Brianti, F
机构：
[1] Silicon Syst Design Ltd, Dublin 2, Ireland
[2] SGS Thomson Microelect, San Jose, CA 95110 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 07期
关键词：
BiCMOS; booth recoding; FIR; 4 : 2 compressor; hard-disk drive; multiplier; partial product; Wallace tree;
D O I：
10.1109/4.701282
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-sample per cycle, programmable five-tap, area-efficient finite-impulse response (FLR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 mu W/MHz [6] with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques.
引用
收藏
页码：1134 / 1138
页数：5
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