High performance timing-driven rank filter

被引：1

作者：

Szanto, Peter ^{[1
]}

Feher, Bela ^{[1
]}

Szedo, Gabor ^{[2
]}

机构：

[1] Budapest Univ Technol & Econ, Dept Measurement & Informat Syst, Budapest, Hungary

[2] Xilinx Inc, San Jose, CA 95124 USA

来源：

2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年

关键词：

D O I：

10.1109/ICECS.2006.379898

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

引用

页码：752 / +

页数：2

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