Fully integrated 56 nm DRAM technology for 1 gb DRAM

被引：14

作者：

Park, Y. K. ^{[1
]}

Lee, S. H. ^{[1
]}

Lee, J. W. ^{[1
]}

Lee, J. Y. ^{[1
]}

Han, S. H. ^{[1
]}

Lee, E. C. ^{[1
]}

Kim, S. Y. ^{[1
]}

Han, J. ^{[1
]}

Sung, J. H. ^{[1
]}

Cho, Y. J. ^{[1
]}

Jun, J. Y. ^{[1
]}

Lee, D. J. ^{[1
]}

Kim, K. H. ^{[1
]}

Kim, D. K. ^{[1
]}

Yang, S. C. ^{[1
]}

Song, B. Y. ^{[1
]}

Sung, Y. S. ^{[1
]}

Byun, H. S. ^{[2
]}

Yang, W. S. ^{[1
]}

Lee, K. H. ^{[1
]}

Park, S. H. ^{[1
]}

Hwang, C. S. ^{[1
]}

Chung, T. Y. ^{[1
]}

Lee, W. S. ^{[1
]}

机构：

[1] Samsung Elect Co, Adv Technol Dev, Semicond R&D Ctr, San 16 Banwoel Dong, Hwaseong City, Kyungki Do, South Korea

[2] Samsung Elect Co, CAE, Semicond R&D Ctr, Hwaseong City, Kyungki Do, South Korea

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339688

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 56 nm feature sized 1 Gb DRAM technology is successfully developed using ArF immersion lithography with a novel integration scheme. The cell size is 0.019 mu m(2), which is the smallest one ever reported. In order to achieve high performance transistor characteristics with scaled down channel length, gate electrode is changed with dual poly tungsten metal gate, as well as elevated source-drain area with Selective Epitaxial Growth (SEG) Si layer. For the data retention of DRAM cell, Asymmetric Channel doping (ASC) is more localized through the data node contact of the cell transistor. High aspect ratio OCS structure and ZAZ dielectric scheme were developed for high cell capacitance.

引用

页码：190 / +

页数：2

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