A highly scalable 3D chip for binary neural network classification applications

被引:0
|
作者
Bermak, A [1 ]
机构
[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 x 2 x 0.7) cm(3). The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2mus for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2mus for any 16-it precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.
引用
收藏
页码:685 / 688
页数:4
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