A highly scalable 3D chip for binary neural network classification applications

被引:0
|
作者
Bermak, A [1 ]
机构
[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 x 2 x 0.7) cm(3). The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2mus for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2mus for any 16-it precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.
引用
收藏
页码:685 / 688
页数:4
相关论文
共 50 条
  • [1] Scalable Binary Neural Network Applications in Oblivious Inference
    Zhang, Xinqiao
    Samragh, Mohammad
    Hussain, Siam
    Huang, Ke
    Koushanfar, Farinaz
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2024, 23 (03)
  • [2] Reconfigurable Network-on-Chip for 3D Neural Network Accelerators
    Firuzan, Arash
    Modarressi, Mehdi
    Daneshtalab, Masoud
    Reshadi, Midia
    2018 TWELFTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2018,
  • [3] Binary Classification of Images for Applications in Intelligent 3D Scanning
    Vezilic, Branislav
    Gajic, Dusan B.
    Dragan, Dinu
    Petrovic, Veljko
    Mihic, Srdan
    Anisic, Zoran
    Puhalac, Vladimir
    INTELLIGENT DISTRIBUTED COMPUTING XI, 2018, 737 : 199 - 209
  • [4] Hybrid network model based on 3D convolutional neural network and scalable graph convolutional network for hyperspectral image classification
    Wang, Xili
    Liang, Zhengyin
    IET IMAGE PROCESSING, 2023, 17 (01) : 256 - 273
  • [5] TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
    Gao, Mingyu
    Pu, Jing
    Yang, Xuan
    Horowitz, Mark
    Kozyrakis, Christos
    OPERATING SYSTEMS REVIEW, 2017, 51 (02) : 751 - 764
  • [6] TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
    Gao, Mingyu
    Pu, Jing
    Yang, Xuan
    Horowitz, Mark
    Kozyrakis, Christos
    ACM SIGPLAN NOTICES, 2017, 52 (04) : 751 - 764
  • [7] TETRIS: Scalable and efficient neural network acceleration with 3D memory
    Gao M.
    Pu J.
    Yang X.
    Horowitz M.
    Kozyrakis C.
    1600, Association for Computing Machinery, 2 Penn Plaza, Suite 701, New York, NY 10121-0701, United States (52): : 751 - 764
  • [8] TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
    Gao, Mingyu
    Pu, Jing
    Yang, Xuan
    Horowitz, Mark
    Kozyrakis, Christos
    TWENTY-SECOND INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS XXII), 2017, : 751 - 764
  • [9] A neural network approach to the classification of 3D prismatic parts
    Wu, MC
    Jen, SR
    INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 1996, 11 (05): : 325 - 335
  • [10] Efficient binary 3D convolutional neural network and hardware accelerator
    Li, Guoqing
    Zhang, Meng
    Zhang, Qianru
    Lin, Zhijian
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2022, 19 (01) : 61 - 71