A novel global self-timing methodology for BSFQ circuits

被引:3
|
作者
Teh, CK [1 ]
Okabe, Y [1 ]
机构
[1] Univ Tokyo, Dept Elect Engn, Tokyo 1138656, Japan
关键词
asynchronous design; Boolean primitive; BSFQ; pipelining; self-timing; SFQ circuits;
D O I
10.1109/TASC.2003.813931
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Recently we have proposed Boolean single-flux-quantum (BSFQ) circuits, which like CMOS circuits directly support Boolean primitives, and do not require local synchronization for their elementary cells as well as for their combinational cells. However, only the cell-level timing description of the BSFQ circuits was considered, which did not specify their global timing strategy in a system-level design. In this paper, we present a novel global self-timing methodology, dual encoding hierarchical pipelining (DEHP), for the locally asynchronous BSFQ circuits. In circuit implementation, a nonvolatile memory cell named ND-DFF and a volatile memory cell named D-DFF have been designed.
引用
收藏
页码:543 / 546
页数:4
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