Variation-Aware Deep Nanometer Gate Performance Modeling: An Analytical Approach

被引：0

作者：

Chen, Min ^{[1
]}

Yi, Yang ^{[2
]}

Zhao, Wei ^{[1
]}

Ma, Dian ^{[3
]}

机构：

[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85281 USA

[2] Texas A&M Univ, Dept Elect & Comp Engn, College Stn, TX 77843 USA

[3] Missouri Univ Sci & Technol, Dept Elect & Comp Engn, Rolla, MO 65409 USA

来源：

2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2011年

关键词：

DELAY;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A complete set of analytical gate performance models is developed based on driving current analysis. Closed-form equations for gate delay and output slew are obtained, which capture the dependence on key process and design parameters, such as the input slew, threshold voltage, etc. Using these formulas, gate performance of various topologies is accurately predicted under both nominal and variational conditions. This work can be easily implemented to enhance fast statistical timing analysis, circuit optimization and aging characterization.

引用

页码：410 / 413

页数：4

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