Design of a Hybrid Multicore Platform for High Performance Reconfigurable Computing

This paper presents a loosely-coupled, hybrid architecture of homogeneous and heterogeneous cores integrated together over a Network-on-Chip (NoC). The architecture efficiently utilizes the NoC bandwidth by keeping a balance between the instantiated number of computational and communication nodes. Furthermore, the architecture also provides a mixed flavor of homogeneous general-purpose processing and heterogeneous reconfigurable computing. Prior approaches have mostly considered homogeneous and heterogeneous platforms as two different design paradigms despite both show domain-specific performance advantages over each other. In this context, the proposed architecture is designed for nine NoC nodes, arranged in a topology of three rows and three columns. The middle row contains three homogeneous Reduced Instruction Set Computer (RISC) cores and rest of the nodes are integrated with Coarse-Grain Reconfigurable Arrays (CGRAs) of application-specific sizes. The overall architecture is template-based which can be crafted to application's performance requirements. The NoC allows loose coupling, so all the cores can mutually exchange the data as well as enable independent and simultaneous execution. Contrarily, the user can program the middle layer of RISC cores for specific data/control dependencies among all the cores. The system mitigates power dissipation as the CGRAs are custom tailored for heterogeneous computing. The platform is evaluated for a proof-of-concept test comprising of massively-parallel signal processing algorithms. Synthesis results from a Field Programmable Gate Array device are used to establish comparisons and evaluation against some of the existing state-of-the-art multicore platforms in terms of multiple performance metrics.