Low switching noise CMOS circuit design strategy based on regular self-timed structures

被引：1

作者：

González, JL ^{[1
]}

Rubio, A ^{[1
]}

机构：

[1] Univ Politecn Catalunya, Dept Elect Engn, ES-08034 Barcelona, Spain

来源：

1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/MWSCAS.1998.759463

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a new design strategy used to implement low switching noise digital circuits is presented. The switching noise reduction is achieved by controlling the shape of the switching current waveform of the CMOS logic circuits. Self-timed structures are required to obtain the wanted switching current waveform shape. Current limiters cue also rued to control the current waveform amplitude of the single cells of the structure. The design strategy proposed is applied to a circuit example, a 4x4 unsigned array multiplier, and experimental results are presented.

引用

页码：176 / 179

页数：4

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