A low voltage current reuse LNA in a 130nm CMOS technology for UWB applications

被引：14
|
作者：
Taris, T. [1 ]
Begueret, J. B. [1 ]
Deval, Y. [1 ]
机构：
[1] Univ Bordeaux 1, IXL Lab, F-33405 Talence, France
来源：
2007 EUROPEAN MICROWAVE CONFERENCE, VOLS 1-4 | 2007年
关键词：
D O I：
10.1109/EUMC.2007.4405391
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A resistive current reuse UWB LNA implemented in a 130 nm CMOS technology is here reported. Covering a 2 to 9 GHz band, the circuit provides an 11.5 dB gain for a 4.45 dB minimum noise figure. Across the frequency band of interest, the NF is kept below 9 dB. The broadband behaviour of the input stage allows achieving a very wide input matching. As well Sit is lower than -12dB from 1 to 14.8GHz while bias current of reuse limits power consumption of the LNA core to 12 mA under 1.4V supply voltage. The chip size is here 0.63mm(2) including pads, thus depicting the lowest silicon area reported in the state of the art for such UWB LNA.
引用
收藏
页码：1105 / 1108
页数：4
相关论文
共 50 条
  • [11] A 0.65V, linearized cascade UWB LNA by application of modified derivative superposition technique in 130nm CMOS technology
    Rafati, Maryam
    Qasemi, Seyed Ruhallah
    Amiri, Parviz
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 99 (03) : 693 - 706
  • [12] 3-5 GHz CMOS Power Amplifier in 130nm CMOS for UWB Applications
    El-Feky, Nagham G.
    Ellaithy, Dina M.
    Fedawy, Mostafa
    2022 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONICS ENGINEERING (ICEEE 2022), 2022, : 32 - 35
  • [13] Ultra-Low-Voltage Driver for Large Load Capacitance in 130nm CMOS Technology
    Sovcik, Michal
    Kovac, Martin
    Arbet, Daniel
    Stopjakova, Viera
    2017 20TH IEEE INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUIT & SYSTEMS (DDECS), 2017, : 127 - 132
  • [14] Enhanced UWB CS-LNA with Inverse Filter and Shunt Feedback Resistor in 130nm CMOS
    Abedi, O.
    Yagoub, M. C. E.
    Abedi, A.
    2009 3RD INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2009), 2009, : 104 - 109
  • [15] Low Power High-Speed Current Comparator Using 130nm CMOS Technology
    Badal, Md Torikul Islam
    Bin Mashuri, Mujahidun
    Reaz, Mamun Bin Ibne
    Kamal, Noorfazila
    Hashim, Fazida Hanim
    2016 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL, ELECTRONIC AND SYSTEMS ENGINEERING (ICAEES), 2016, : 72 - 76
  • [16] Low-Leakage ESD Structures in 130nm CMOS Technology
    Nagy, Lukas
    Chvala, Ales
    Stopjakova, Viera
    PROCEEDINGS OF THE 2020 30TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA), 2020, : 177 - 180
  • [17] Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology
    Muhamad, M.
    Soin, N.
    Ramiah, H.
    INTERNATIONAL CONFERENCE ON APPLIED ELECTRONIC AND ENGINEERING 2017 (ICAEE2017), 2018, 341
  • [18] A New UWB LNA with 15 dB Gain in 90 nm CMOS with Current Reuse topology
    Khavari, Amir Farzad
    Mafinezhad, Khalil
    26TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE 2018), 2018, : 184 - 189
  • [19] A wideband LNA for wireless multistandard receiver in 130nm CMOS SOI process
    Martineau, B.
    Tinella, C.
    Gianesello, F.
    Cathelin, A.
    Belot, D.
    Danneville, F.
    Kaiser, A.
    PRIME 2006: 2ND CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONIC AND ELECTRONICS, PROCEEDINGS, 2006, : 449 - +
  • [20] A 130nm CMOS Polar Quantizer for Cellular Applications
    Nazari, Peyman
    Chun, Byung-Kwan
    Kumar, Vipul
    Middleton, Eric
    Wang, Zheng
    Heydari, Payam
    2013 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), 2013, : 155 - 158
12345