On-Chip Hardware Accelerators for Data Processing and Combinatorial Search

被引:0
|
作者
Sklyarov, Valery [1 ]
Skliarova, Iouliia [1 ]
机构
[1] Univ Aveiro, Dept Elect Telecommun & Informat IEETA, Aveiro, Portugal
关键词
Data processing; combinatorial search; high-performance computing; parallelism; programmable systems-on-chip; IMPLEMENTATION;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Data processing and combinatorial search are widely used techniques in the scope of information and communication. Examples of practical applications are sorting, frequent items encountering, matrix/set covering, graph/map coloring, data mining, priority management, and many others. Often information/data processing that involves the listed above tasks has to be done in embedded systems where high performance needs to be achieved in portable and low-cost devices integrating multiple functions and capabilities. An efficient development technique for such systems is hardware/software co-design with the use of programmable systems-on-chip that are highly integrated, easily customizable/configurable and permit broad parallelism to be supported that is the primary way to accelerate computations. The tutorial is dedicated to such a design technique.
引用
收藏
页码:52 / 56
页数:5
相关论文
共 50 条
  • [1] On-Chip Reconfigurable Hardware Accelerators for Popcount Computations
    Sklyarov, Valery
    Skliarova, Iouliia
    Silva, Joao
    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2016, 2016
  • [2] On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators
    Carsten Heinz
    Andreas Koch
    Journal of Signal Processing Systems, 2022, 94 : 883 - 893
  • [3] On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators
    Heinz, Carsten
    Koch, Andreas
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2022, 94 (09): : 883 - 893
  • [4] Efficient Data Streaming with On-chip Accelerators: Opportunities and Challenges
    Hou, Rui
    Zhang, Lixin
    Huang, Michael C.
    Wang, Kun
    Franke, Hubertus
    Ge, Yi
    Chang, Xiaotao
    2011 IEEE 17TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2011, : 312 - 320
  • [5] Hardware Accelerators for Data Sort in All Programmable Systems-on-Chip
    Sklyarov, Valery
    Skliarova, Iouliia
    ADVANCES IN ELECTRICAL AND COMPUTER ENGINEERING, 2015, 15 (04) : 9 - 16
  • [6] Hardware Accelerators for Data Processing in High Performance Computing Systems
    Sklyarov, Valery
    Skliarova, Iouliia
    Utepbergenov, Irbulat
    2021 IEEE 15TH INTERNATIONAL CONFERENCE ON APPLICATION OF INFORMATION AND COMMUNICATION TECHNOLOGIES (AICT2021), 2021,
  • [7] Architecture Customization of On-Chip Reconfigurable Accelerators
    Yoon, Jonghee W.
    Lee, Jongeun
    Park, Sanghyun
    Kim, Yongjoo
    Lee, Jinyong
    Paek, Yunheung
    Cho, Doosan
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2013, 18 (04)
  • [8] Designing On-Chip Networks for Throughput Accelerators
    Bakhoda, Ali
    Kim, John
    Aamodt, Tor M.
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2013, 10 (03)
  • [9] MIPS on-chip debug hardware
    不详
    ELECTRONIC DESIGN, 2001, 49 (20) : 69 - 69