Double Enhance Dielectric Layer Electric Field High Voltage SOI LDMOS

被引：0
|
作者：
Yang, X. M. [1 ]
Zhang, B. [1 ]
Luo, X. R. [1 ]
机构：
[1] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Peoples R China
来源：
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2011年
关键词：
Back-gate; breakdown voltage; double enhance dielectric layer electric field; p-type layer; shield-trench; silicon-on-insulator LDMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A Double Enhance Dielectric Layer Electric Field (Double ENDIF) silicon-on-insulator (SOI) LDMOS is proposed for high breakdown voltage (BV). The electric field in the buried oxide at the source and drain sides is enhance by charges in shield-trench at positive back-gate bias, resulting to improve the BV. The electric characteristic of the new structure is research by 2D MECICI. Simulation result shows that BV of the new structure reaches 1025 V at 4 mu m and 1 mu m thickness of the silicon and buried oxide layers respectively.
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页数：2
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