A low-power DSP core architecture for low bitrate speech CODEC

被引：0
|
作者：
Okuhata, H [1 ]
Miki, MH [1 ]
Onoye, T [1 ]
Shirakawa, I [1 ]
机构：
[1] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 565, Japan
来源：
PROCEEDINGS OF THE 1998 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-6 | 1998年
关键词：
D O I：
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中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, anti two-banked on-chip memory. The proposed DSP architecture has been integrated in the total area of 7.75 mm(2) by using a 0.35 mu m CMOS technology, which can operate at 10MHz with the dissipation of 45mW from a single 3V supply.
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页码：3121 / 3124
页数：4
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