The restriction on delta-I noise along the power/ground layer in the highspeed digital printed circuit board

In the highspeed digital printed circuit board (PCB), there exists a layer capacitance (generally from 0.02nF to 200nF) between the closely spaced power and ground layers, which has some restriction on delta-I noise. According to MPIE (Mixed Potential Integral Equation), a model is developed to analyze and characterize quantitatively the restriction on delta-I noise by the power/ground structure in PCB in high frequencies (from 100MHz to 3GHz). In comparison with the measured data from a testboard, the method produces relatively precise results. The restriction on delta I noise is complicated by the high frequency. And several strategies are provided to reduce the noise.