The restriction on delta-I noise along the power/ground layer in the highspeed digital printed circuit board

被引：0
|
作者：
Ren, KN [1 ]
Wu, CY [1 ]
Zhang, LC [1 ]
机构：
[1] Jiao Tong Univ, Dept Telecom & Control Engn, EMC Res Sect, Beijing 100044, Peoples R China
来源：
1998 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY - SYMPOSIUM RECORD, VOLS 1 AND 2 | 1998年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In the highspeed digital printed circuit board (PCB), there exists a layer capacitance (generally from 0.02nF to 200nF) between the closely spaced power and ground layers, which has some restriction on delta-I noise. According to MPIE (Mixed Potential Integral Equation), a model is developed to analyze and characterize quantitatively the restriction on delta-I noise by the power/ground structure in PCB in high frequencies (from 100MHz to 3GHz). In comparison with the measured data from a testboard, the method produces relatively precise results. The restriction on delta I noise is complicated by the high frequency. And several strategies are provided to reduce the noise.
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收藏
页码：511 / 516
页数：6
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