On fault-simulation through embedded memories on large industrial designs

被引：0

作者：

Yadavalli, S ^{[1
]}

Kundu, S ^{[1
]}

机构：

[1] Intel Corp, Test Technol, Santa Clara, CA 95051 USA

来源：

VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN | 2001年

关键词：

fault simulation; memory differential; ATPG; test; embedded memory array; microprocessor;

D O I：

10.1109/ICVD.2001.902649

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modern microprocessor designs contain several embedded memory arrays that form register files, caches, TLBs, Re-order buffers, etc. These arrays are an integral portion of the design and may sometimes drive substantial data-path and control logic blocks in a microprocessor. Fault-simulation and ATPG for state-of-the-art commercial microprocessor designs is complex and requires suitable engineering to make them successful. In this paper we discuss a framework for Fault-simulation of large microprocessor designs containing hundreds of embedded memory arrays which is in use today. Embedded memory arrays come in a variety of flavours with different number of input and output ports and different access mechanisms. In this paper we discuss how these arrays can be described for the fault-simulator and present the data-structures and some of the algorithms for simulating faults through these arrays.

引用

页码：117 / 121

页数：5

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