Germanium Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated by Complementary-Metal-Oxide-Semiconductor-Compatible Process

被引：11

作者：

Peng, J. W. ^{[1
,2
]}

Singh, N. ^{[2
]}

Lo, G. Q. ^{[2
]}

Bosman, M. ^{[2
]}

Ng, C. M. ^{[3
]}

Lee, S. J. ^{[1
]}

机构：

[1] Natl Univ Singapore, Silicon Nano Device Lab, Singapore 119260, Singapore

[2] ASTAR, Inst Microelect, Singapore 117685, Singapore

[3] GLOBALFOUNDRIES, Singapore 738406, Singapore

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2011年 / 58卷 / 01期

关键词：

Core/shell (C/S); germanium (Ge); metal-oxide-semiconductor field-effect transistor (MOSFET); nanowire (NW); top-down; BACKSCATTERING CHARACTERISTICS; PERFORMANCE; SI; PMOSFETS; GROWTH;

D O I：

10.1109/TED.2010.2088125

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a complementary metal-oxide-semiconductor-compatible top-down fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent I-ON/I-OFF ratios (> 10(6)), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm(2)V(-1) . s(-1).

引用

页码：74 / 79

页数：6

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