Design and Analysis for 3D Vertical Resistive Random Access Memory Structures with Silicon Bottom Electrodes

被引:0
|
作者
Kim, Tae-Hyeon [1 ,2 ]
Kim, Sungjun [1 ,2 ]
Kim, Min-Hwi [1 ,2 ]
Cho, Seongjae [3 ]
Park, Byung-Gook [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 141744, South Korea
[2] Seoul Natl Univ, ISRC, Seoul 141744, South Korea
[3] Gachon Univ, Dept Elect Engn, 1342 Seongnam Daero, Seongnam Si 461741, Gyeonggi Do, South Korea
基金
新加坡国家研究基金会;
关键词
3D Vertical Structure; Si3N4 Based RRAM; Resistive Switching; LOW-POWER;
D O I
10.1166/jnn.2017.14760
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
In this work, we propose two 3D vertical RRAM structures and their detailed fabrication methods. One is a double-horizontal-electrode (DHE) structure where a top electrode covers both sides of a silicon bottom electrode, and the other is a gate-all-around (GAA) structure where silicon nanowires are enclosed by resistive switching layers and resistive switching layers are enclosed by top electrodes. In these two 3D vertical structures, the chemical vapor deposition (CVD) process is essential for deposition of a resistive switching layer and a top electrode material, and heavily doped silicon should be applied as a bottom electrode. Several advantages of resistive random access memory (RRAM) with metal-insulator-semiconductor (MIS) structure are also investigated. Furthermore, we fabricated a W/Si3N4/n+-doped-polysilicon RRAM device, composed of suitable materials for the proposed 3D RRAM structures and investigated its resistive switching characteristics.
引用
收藏
页码:7160 / 7163
页数:4
相关论文
共 50 条
  • [31] Ni-Containing Electrodes for Compact Integration of Resistive Random Access Memory With CMOS
    Wang, X. P.
    Fang, Z.
    Chen, Z. X.
    Kamath, A. R.
    Tang, L. J.
    Lo, G-Q
    Kwong, D-L
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (04) : 508 - 510
  • [32] Effects of Electrodes on the Switching Behavior of Strontium Titanate Nickelate Resistive Random Access Memory
    Lee, Ke-Jing
    Wang, Li-Wen
    Chiang, Te-Kung
    Wang, Yeong-Her
    MATERIALS, 2015, 8 (10): : 7191 - 7198
  • [33] Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory
    Yue Bai
    Huaqiang Wu
    Riga Wu
    Ye Zhang
    Ning Deng
    Zhiping Yu
    He Qian
    Scientific Reports, 4
  • [34] Realization of Vertical Resistive Memory (VRRAM) using cost effective 3D Process
    Baek, I. G.
    Park, C. J.
    Ju, H.
    Seong, D. J.
    Ahn, H. S.
    Kim, J. H.
    Yang, M. K.
    Song, S. H.
    Kim, E. M.
    Park, S. O.
    Park, C. H.
    Song, C. W.
    Jeong, G. T.
    Choi, S.
    Kang, H. K.
    Chung, C.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [35] Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory
    Bai, Yue
    Wu, Huaqiang
    Wu, Riga
    Zhang, Ye
    Deng, Ning
    Yu, Zhiping
    Qian, He
    SCIENTIFIC REPORTS, 2014, 4
  • [36] Architecting 3D Vertical Resistive Memory for Next-Generation Storage Systems
    Xu, Cong
    Chen, Pai-Yu
    Niu, Dimin
    Zheng, Yang
    Yu, Shimeng
    Xie, Yuan
    2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2014, : 55 - 62
  • [37] Analysis of conductive filament density in resistive random access memories: a 3D kinetic Monte Carlo approach
    Aldana, Samuel
    Garcia-Fernandez, Pedro
    Romero-Zaliz, Rocio
    Jimenez-Molinos, Francisco
    Gomez-Campos, Francisco
    Bautista Roldan, Juan
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2018, 36 (06):
  • [38] Susceptibility Evaluation of 3D Integrated Static Random Access Memory with Through-Silicon Vias (TSVs)
    Cao, Xue-Bing
    Xiao, Li-Yi
    Zhang, Rong-Sheng
    Li, Jia-Qiang
    Li, Hong-Chen
    Wang, Jin-Xiang
    17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
  • [39] Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory
    黄达
    吴俊杰
    唐玉华
    Chinese Physics B, 2013, 22 (03) : 526 - 531
  • [40] Electrothermal Effects on Reliability of Vertical Resistive Random Access Memory Array by Parallel Computing
    Xie, Hao
    Zhu, Guodong
    Xu, Xingxing
    Zhang, Shuo
    Yin, Wen-Yan
    Chen, Wenchao
    Chen, Yazhou
    Chen, Jixin
    2019 12TH INTERNATIONAL WORKSHOP ON THE ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2019), 2019, : 287 - 289