Logic verification of very large circuits using shark

被引：9

作者：

Casas, J ^{[1
]}

Yang, H ^{[1
]}

Khaira, M ^{[1
]}

Joshi, M ^{[1
]}

Tetzlaff, T ^{[1
]}

Otto, S ^{[1
]}

Seligman, E ^{[1
]}

机构：

[1] Intel Corp, CAD Labs, Santa Clara, CA 95051 USA

来源：

TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/ICVD.1999.745167

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we will present Shark, a software based logic verification technology that allows high-performance switch-level simulation of multi-million transistor circuits on general-purpose workstations. Shark achieves high-performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect any number of simulators to form, a distributed/parallel simulation environment. Shark has been tested on circuits of up to 15M transistors. On an Intel circuit with about 5M transistors, Shark achieved a simulation throughput of 19 Hz.

引用

页码：310 / 317

页数：8

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