A scalable and pipelined FPGA implementation of an OC192WF scheduler

被引：0
|
作者：
Merhebi, A [1 ]
Mohamed, OA [1 ]
机构：
[1] Concordia Univ, ECE Dept, Montreal, PQ, Canada
来源：
2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/FPT.2004.1393308
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for POS interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions is two folds: First, we have combined the Highest Value First scheme and the Round Robin scheme into a single pipelined design able to schedule traffic for 4 channels in parallel. Second, we showed how to build higher order WF queuing system without decreasing the overall performance of our scheduler. As a result, our scheduler is general enough to accommodate ATM (UTOPIA L3/L4), POS/PL3 (OC48) as well as POS/PL4 (OC192) interfaces.
引用
收藏
页码：395 / 398
页数：4
相关论文
共 50 条
  • [31] SAccO: An implementation platform for scalable FPGA accelerators
    Weinhardt, Markus
    Lang, Bernhard
    Thiesing, Frank M.
    Krieger, Alexander
    Kinder, Thomas
    MICROPROCESSORS AND MICROSYSTEMS, 2015, 39 (07) : 543 - 552
  • [32] FPGA implementation(s) of a scalable encryption algorithm
    Mace, F.
    Standaert, F. -X.
    Quisquater, J. -J.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (02) : 212 - 216
  • [33] FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters
    Wang, Tianqi
    Geng, Tong
    Li, Ang
    Jin, Xi
    Herbordt, Martin
    IEEE TRANSACTIONS ON COMPUTERS, 2020, 69 (08) : 1143 - 1158
  • [34] Matrix Multiplication based on Scalable Macro-Pipelined FPGA Accelerator Architecture
    Jiang, Jiang
    Mirian, Vincent
    Tang, Kam Pui
    Chow, Paul
    Xing, Zuocheng
    2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS, 2009, : 48 - +
  • [35] A scalable hardware implementation of a best-effort scheduler for multicore processors
    Gregorek, Daniel
    Osewold, Christof
    Garcia-Ortiz, Alberto
    16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 721 - 727
  • [36] Scalable implementation of ANNs on linear array with a reconfigurable pipelined bus system
    Cong, B
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOL VI, PROCEEDINGS, 1999, : 2863 - 2869
  • [37] Pipelined FPGA Implementation of Numerical Integration of the Hodgkin-Huxley Model
    Osorio, Roberto R.
    2016 IEEE 27TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), 2016, : 202 - 206
  • [38] Performance characteristics of parallel and pipelined implementation of FIR filters in FPGA platform
    Deepak, G.
    Meher, P. K.
    Sluzek, A.
    ISSCS 2007: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2007, : 245 - +
  • [39] A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division
    Monteiro, F
    Dandache, A
    M'Sir, A
    Lepley, B
    ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 1231 - 1234
  • [40] A Real-time, Pipelined Incoherent Dedispersion Method and Implementation in FPGA
    Liu, Wei
    Meng, Qiao
    Wang, Chen
    Zhou, Chenye
    Yao, Shunyu
    Tariq, Irfan
    PUBLICATIONS OF THE ASTRONOMICAL SOCIETY OF THE PACIFIC, 2022, 134 (1031)
12345