Thin gate, dielectric TFTs using damascene-gate structures

As flat panel display sizes and resolutions increase, it becomes necessary to improve the electronic performance of the TFT array. This requires the use of low-resistance gate lines and faster switching TFTs, which can be achieved by using thick gate metal and thin gate dielectrics, respectively. However, in conventional inverted-staggered devices, thick gates create a large step which then requires a thick gate dielectric for adequate coverage. The approach presented here embeds the gate in a passivation layer so that thin gate dielectrics can be deposited on a relatively flat surface. More importantly, this structure is achieved without increasing the number of masks used in conventional processes and does not require any chemical-mechanical polishing of the surface. Profilometry reveals a smooth surface with step mismatch as low as 10 nm. Gate dielectrics as thin as 50 nm were deposited and excellent TFT performance is obtained.