Simulated Annealing Based Thermal-aware Floorplanning

被引：0

作者：

Qi, Lixia ^{[1
]}

Xia, Yinshui ^{[1
]}

Wang, Lunyao ^{[1
]}

机构：

[1] Ningbo Univ, Inst Circuits & Syst, Ningbo 315211, Zhejiang, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC) | 2011年

关键词：

thermal aware; SoC; power density; floorplanning; Simulated Annealing;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a simulated annealing based thermal-aware floorplanning for SoC design. The proposed method is applied to MCNC benchmark circuits, the results show that the temperature for MCNC hp can be reduced up to 23 degrees C.

引用

页码：463 / 466

页数：4

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