Simulated Annealing Based Thermal-aware Floorplanning

被引：0
|
作者：
Qi, Lixia [1 ]
Xia, Yinshui [1 ]
Wang, Lunyao [1 ]
机构：
[1] Ningbo Univ, Inst Circuits & Syst, Ningbo 315211, Zhejiang, Peoples R China
来源：
2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC) | 2011年
关键词：
thermal aware; SoC; power density; floorplanning; Simulated Annealing;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a simulated annealing based thermal-aware floorplanning for SoC design. The proposed method is applied to MCNC benchmark circuits, the results show that the temperature for MCNC hp can be reduced up to 23 degrees C.
引用
收藏
页码：463 / 466
页数：4
相关论文
共 50 条
  • [11] Interconnect and thermal-aware floorplanning for 3D microprocessors
    Hung, W. -L.
    Link, G. M.
    Xie, Yuan
    Vijaykrishnan, N.
    Irwin, M. J.
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 98 - +
  • [12] Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
    Ma, Yuchun
    Li, Xin
    Wang, Yu
    Hong, Xianlong
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (12): : 2979 - 2989
  • [13] A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models
    Lin, Jai-Ming
    Chen, Tai Ting
    Chang, Yen-Fu
    Chang, Wei-Yi
    Shyu, Ya-Ting
    Chang, Yeong-Jar
    Lu, Juin-Ming
    2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,
  • [14] Fixed-outline Thermal-aware 3D Floorplanning
    Xiao, Linfu
    Sinha, Subarna
    Xu, Jingyu
    Young, Evangeline F. Y.
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 552 - +
  • [15] The Thermal-aware Floorplanning for 3D ICs using carbon nanotube
    Shi, Shengqing
    Zhang, Xi
    Luo, Rong
    PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1155 - 1158
  • [16] Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels
    Zajac, Piotr
    Galicia, Melvin
    Napieralski, Andrzej
    PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2018), 2018, : 258 - 261
  • [17] Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation
    Lin, Jai-Ming
    Chen, Tai-Ting
    Hsieh, Hao-Yuan
    Shyu, Ya-Ting
    Chang, Yeong-Jar
    Lu, Juin-Ming
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (05) : 985 - 997
  • [18] An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning
    Chen, Jianli
    Liu, Yan
    Zhu, Ziran
    Zhu, Wenxing
    INTEGRATION-THE VLSI JOURNAL, 2017, 58 : 245 - 252
  • [19] Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs
    Jang, Cheoljon
    Chong, Jong-who
    ETRI JOURNAL, 2014, 36 (04) : 634 - 641
  • [20] Modern floorplanning based B*-tree and fast simulated annealing
    Chen, TC
    Chang, YW
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (04) : 637 - 650
12345