An FPGA-based ATE Extension Module for Low-Cost Multi-GHz Memory Test

被引：0

作者：

Keezer, D. C. ^{[1
]}

Chen, T. H. ^{[1
]}

Moon, T. ^{[1
]}

Stonecypher, D. T. ^{[1
]}

Chatterjee, A. ^{[1
]}

Choi, H. W. ^{[2
]}

Kim, S. Y. ^{[2
]}

Yoo, H. ^{[2
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Samsung Elect Co, Suwon, South Korea

来源：

2015 20TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2015年

关键词：

ATE; FPGA; MemoryTest; Multi-GHz;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost "host" test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel "pin electronics" (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a "shadow sampler."

引用

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